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tm data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7677 or 7381 features ? small size (3.0" x 2.1" x 0.39") +200 v and +500 v capability 30 a current capability high-efficiency mosfet or igbt drive stage direct drive from commutation logic six step trapezoidal or sinusoidal drive four quadrant operation 0.85 c/w j-c max military processing available description the pwr-82331 and PWR-82333 are 30 a, 3-phase motor drive hybrids. the pwr-82331 has a +200 v rating and uses mosfets in the output stage while the PWR-82333 has a +500 v rating and an igbt output stage. both types have individual fast recovery diodes internally connected across the output drive transistors to clamp inductive flyback. these smart power motor drives have cmos schmitt trigger inputs for high noise immunity. high- and low-side input logic signals are xor?d in each phase to prevent simultaneous turn-on of in-line transistors, thus eliminating a shoot through condition. the internal logic controls the high- and low-side gate drives for each phase and can operate from +5 to +15 v logic levels. the internal power supply provides a constant volt- age source to the floating high-side gate drives, and constant output per- formance for switching frequencies from dc to 50 khz. applications these hybrids are an excellent choice for high-performance, high-reli- ability motor drives for military and aerospace servo-amps and speed controls. among the many applications are robotics; electro-mechan- ical valve assemblies; actuator systems for flight control surfaces on military and commercial aircraft; antenna and radar positioning; fan and blower motors for environmental conditioning; thrust and vector position control of mini-subs, drones, and rpv?s; compressor motors for cryogenic coolers; and high power inverters. the pwr-82331/82333 hybrids are ideal for harsh military environments where shock, vibration, and temperature extremes are evident, such as missile applications where fin actuator systems control missile direction. ? 1998, 1999 data device corporation pwr-82331 and PWR-82333 smart power 3-phase motor drives make sure the next card you purchase has...
2 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 pwr-82331 and PWR-82333 figure 1. pwr-82331/82333 block diagram digital control and protection circuitry
3 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 table 1. pwr-82331 and PWR-82333 absolute maximum ratings (tc = +25c unless otherwise specified) parameter symbol pwr-82331 PWR-82333 units supply voltage v cc 200 500 v bias voltage v b 50 50 v logic power-in voltage v lpi 18 18 v input logic voltage v u , v l , v sd v lpi + 0.5 v lpi + 0.5 v output current continuous pulsed i o i op 30 50 30 50 a a operating frequency fo 50 25 khz case operating temperature t c -55 to +125 -55 to +125 c gnd - vss differential voltage case storage temperature range t cs 3 -55 to +150 3 -55 to +150 vdc-peak c table 2. pwr-82331 and PWR-82333 specifications (tc = +25c unless otherwise specified) parameter symbol test conditions pwr-82331 units PWR-82333 min typ max min max typ output output current continuous (see fig. ? s 15 & 19) supply voltage output on-resistance (each fet)(see fig. 14a) output voltage drop (each igbt) (see fig. 14b) instant forward voltage (flyback diode) (see fig. ? s 13a/b reverse recovery time (flyback diode) reverse leakage current at tc = +25 c reverse leakage current at tc = +125 c i o v cc r on v ce ( sat ) v f trr ir ir see note 1 i o =30 a i o =30 a i op =30 a, see note 2 if=1 a, ir=1 a see note 3 see note 3 28 30 140 0.1 1.15 50 10 1 a v ohm v v nsec a ma 30 350 3.8 1.70 50 10 1 270 bias supply input bias voltage (t c = -55 c to +125 c) quiescent bias current (see note 4)(see fig. 16) bias current (t c = -55 c to +125 c)(see fig. ? s 17 & 18) in-rush current (t c = -55 c to +125 c) logic power input current vb ibq ib iir i lpi vb = 28 v vb=28 v, see note 5 vb = 28 v see note 6 14 35 32 50 65 1.4 2 14 35 v ma ma a ma 50 65 1.4 2 32 input signals (see fig. 7) positive trigger threshold voltage negative trigger threshold voltage hysteresis voltage positive trigger threshold voltage negative trigger threshold voltage hysteresis voltage v p v n v h v p v n v h pin connections pin 15 &16 connect. pin 15 &16 connect. pin 15 &16 connect see note 6 see note 6 see note 6 2.1 1.6 0.9 0.3 12.9 10.8 4.3 3.6 2.1 1.6 0.9 0.3 v v v v v v 12.9 10.8 4.3 3.6 switching characteristics (see fig. 2) upper drive: turn-on propagation delay turn-off propagation delay shut-down propagation delay turn-on rise time turn-off fall time lower drive: turn-on propagation delay turn-off propagation delay shut-down propagation delay turn-on rise time turn-off fall time td(on) td(off) t sd tr tf td(on) td(off) t sd tr tf test 1 conditions pin 15 &16 connect. +15 v logic io=30 a peak pwr-82331, v cc = 140 v PWR-82333, v cc = 270 v 840 1020 800 125 125 850 1000 800 125 125 nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec 810 860 810 100 150 800 870 770 100 150 switching characteristics (see fig. 2) upper drive: turn-on propagation delay turn-off propagation delay shut-down propagation delay turn-on rise time turn-off fall time td(on) td(off) t sd tr tf test 2 conditions see note 6 +5 v, io=30 a peak pwr-82331, vcc = 140 v PWR-82333, v cc = 270 v 1090 1315 1100 125 125 nsec nsec nsec nsec nsec 1050 1150 850 100 150
4 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 table 2. pwr-82331 and PWR-82333 specifications (cont'd) (tc = +25c unless otherwise specified) parameter symbol test conditions pwr-82331 PWR-82333 unit min typ max min typ max switching characteristics (cont?d) lower drive: turn-on propagation delay turn-off propagation delay shut-down propagation delay (see fig. 10) turn-on rise time turn-off fall time td(on) td(off) tsd tr tf test 2 conditions see note 6 +5 v, io=30 a peak pwr-82331, vcc=140 v PWR-82333, 270 v 1125 1290 1100 125 125 1050 1150 850 100 150 nsec nsec nsec nsec nsec dead time tdt 400 500 nsec minimum pulse width tpw 150 150 nsec thermal maximum thermal resistance maximum lead soldering temperature (note 7) junction temperature range case operating temperature case storage temperature jc ts tj tco tcs each transistor -55 -55 -55 0.85 250 150 125 150 -55 -55 -55 0.85 250 150 125 150 c/w c c c c weight 4.9 (140) 4.9 (140) oz (g) notes: 1. for hi-rel applications, derating per mil-s-19500 should be observed. (derate vcc to 70%.) 2. pulse width 300 ms, duty cycle 2%. 3. for pwr-82331, vcc = 140 v, vu, vl = logic ? 0 ? and for PWR-82333, vcc = 350 v, vu, vl = logic ? 0. ? 4. vu, vl = logic ? 0 ? on pins 17,18,20,21,24 and 25. 5. for pwr-82331, fo = 30 khz and for PWR-82333, fo = 10 khz. 6. pin 16 connected to external +5 v supply. 7. solder 1/8 ? from case for 5 seconds maximum. introduction the 3-phase pwr-82331 and PWR-82333 are 30 a motor drive hybrids rated at +200 v and +500 v respectively. the pwr- 82331 uses a mosfet output stage and the PWR-82333 has an igbt output stage for high speed, high current, and high effi- ciency operation. the PWR-82333 also offers high-voltage per- formance of an igbt for use in +270 v systems. these motor drives are ideal for use in high-performance motion control sys- tems, servo amplifiers, and motor speed control designs. furthermore, multi-axis systems requiring multiple drive stages can benefit from the small size of these power drives. the pwr-82331/33 can be driven directly from the commutation logic, dsp, or a custom asic that supplies digital signals to con- trol the upper and lower transistors of each phase. these high- ly integrated drive stages have schmitt trigger digital inputs figure 2. input/output timing relationships 10% that control the high and low side of each phase. digital protec- tion of each phase eliminates an in-line firing condition by pre- venting simultaneous turn-on of both the upper and lower tran- sistors. the logic controls the high- and low-side gate drivers. operation from +5 to +15 v logic levels can be programmed by applying the appropriate voltage to pin 16 (vlpi). the pwr- 82331/333 has a ground referenced low-side gate drive. an internal dc-dc converter supplies a floating output to each side of the three high-side drives. this provides a continuous high-side gate drive even during the motor stall. pin 15 (vlpo) supplies a +15 v output, which can be used to power the internal logic when system usage requires +15 v logic. the high- and low-side gate drivers control the n-channel mosfet or igbt output stage. the mosfets used in the pwr-82331 allow output switching up to 50 khz, while the high-speed igbts in the PWR-82333 can switch at 25 khz. a flyback diode parallels each output transis- tor and controls the regenerative energy produced by the motor. these fast recovery diodes have faster reverse switching times than the intrinsic body diode of the mosfets used in the pwr- 82331. they also protect the igbts used in the PWR-82333 from exceeding their emitter-to-collector breakdown voltage. use of a copper case and solder attachment of the output tran- sistors achieves a low thermal resistance of 0.85 c/w maxi- mum. care should be taken to adequately heatsink these motor drives to maintain a case temperature of 125 c. junction tem- peratures should not exceed 150 c. the pwr-82331/33 do not have internal short-circuit or overcurrent protection. for protec- tion of the output transistors, these features must be added externally to the hybrid. (reference table 2. also.)
5 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 bias voltages the pwr-82331/33 motor drive hybrids require only a single power supply for operation. the hybrid generates three inde- pendent floating supplies, eliminating the need for external bias voltages for each phase. in order for the internal power supply to generate these voltages, the input bias voltage (vb) must be from +15 to +50 vdc. in most avionic systems this can be accomplished by connecting the vb pin to the mil-std-704d, +28 volt bus. see figure 3a. if the system bus voltage is greater than +50 vdc (and a lower voltage is not available), then the vb pin and vz pin can be tied together with an external power resistor (rb) and connected from these pins to the system power bus. (see figure 3b). see figures 4 and 5 for bias resistor characteristics. if additional power dissipation in rb is a concern, figure 3c shows a more efficient design, using a low-power resistor (rt) and an additional transistor. to determine the proper resistor to use, refer to figure 6. if there is another voltage available in the system in the +15 to +50 vdc range, then this voltage can be directly connected to the vb pin of the hybrid. in any case, a 0.01 mf decoupling capacitor (cb) must be connected between vb (pin 12) and gnd. cc figure 3. connection to bus voltage to develop proper input bias voltage 50 cc figure 4a. pwr-82331 figure 4b. PWR-82333 figure 4. bias resistor value (r b ) vs. bus voltage (v cc )
6 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 bus voltage, v (volts) figure 5. power dissipated in bias resistor (r b ) vs. bus voltage (v cc ) figure 6. r t resistor value vs. bus voltage figure 5a. pwr-82331 figure 5b. PWR-82333
7 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 digitally controlled inputs the pwr-82331/33 uses schmitt triggered digital inputs (with hysteresis) to ensure high-noise immunity. the trigger switches at different points for positive and negative going signals. the hysteresis voltage (vh) is the difference between the positive going voltage (vp) and the negative going voltage(vn) (see fig- ure 7). the digital inputs have programmable logic levels, which allows the hybrid to be used with different types of com- mutation logic with an input voltage range of +5 v to +15 v, such as ttl or cmos logic. the pwr-82331/33 internal power sup- ply generates a +15 vdc (vlpo) on pin 15. this output can only be used to power the internal digital circuitry within the hybrid. do not use this +15 v output to power any circuitry external to the hybrid. pin 16 is the logic power input (vlpi) for the dig- ital circuitry inside the hybrid. a 0.01 mf, +50 v ceramic capac- itor must be placed between this pin (16) and gnd as close to the hybrid as possible. when using +15 v control circuitry, the logic power input (pin 16) can be connected directly to logic power output (pin 15) of the hybrid. there is no need for addi- tional external power supply. when using +5 v control logic, an external +5 vdc supply must be connected between pin 16 of the hybrid and the gnd - leave pin 15 open (n/c). the commutation/control cir- cuitry can be as simple as discrete logic with pwm, or as sophis- ticated as a microprocessor or custom asic, depending on the system requirements. the block diagram in figure 8 shows a typical interface of the pwr-82331/33 with a motor and commu- tation logic in a servo-amp system. interfacing with optocouplers optocouplers should be used when the commutation logic can- not be located directly next to the motor drive (within 1"- 2" from the input) or a current sensing resistor is placed between vss and power rtn (see figure 9). the optocouplers minimize the differential ground voltage drop between the logic grounds and the vss connections. optocouplers are also required when +5 v logic is used to control the motor drive. n figure 7. hysteresis definition and characteristics 0.1 f 1 figure 8. pwr-82331/82333 typical interface with a motor and commutation logic
8 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 shut-down input (vsd) pin 23 (vsd) provides a digital shut-down input, which allows the user to completely turn-off both the upper and lower output transistors in all 3-phases. application of a logic ? 1 ? to the vsd input will latch the digital control/protection circuitry thereby turning off all output tran- sistors. the digital control/protection circuitry remains latched in the off-state and will not respond to signals on the vl or vu inputs while the vsd has a logic ? 1 ? applied. when the user or the sense circuitry (as in figure 9) returns the vsd input to a logic ? 0, ? and then the user sets the vl and vu inputs to a logic ? 0 ? the output of the digital control/protection circuitry will clear the internal latch. when the next rising edge (see figure 10) occurs on the vl or vu digital inputs, the output transistors will respond to the corresponding digital input. this feature can be used with external current limit or temperature sense circuitry to disable the drive if a fault condition occurs. internal protection circuitry the hybrid contains digital protection circuitry, which prevents in- line transistors from conducting simultaneously. this, in effect, would short circuit the power supply and would damage the out- put stage of the hybrid. the circuitry allows only proper input sig- nal patterns to cause output conduction. figure 10 and table 3 show these timing relationships. if an improper input requested that the upper and lower transistors of the same phase conduct together, the output would be a high impedance until removal of the illegal code from the input of the pwr-82331/33. a dead time of 500 ns minimum should still be maintained between the signals at the vu and vl pins; this ensures the complete turn off any transistor before turning on its associated in-line transistor. 1 0 1 0 1 0 1 0 1 0 1 0 1 0 h z l h z l h z l figure 10. shut-down (vsd) timing relationships + + hcpl-5230 hcpl-5230 hcpl-5230 hcpl-5200 pwr-82331 +5v 665 665 665 665 665 665 2 2 2 2 7 7 7 5 5 5 8 7 6 5 4 4 4 1 1 1 8 8 8 6 6 6 3 3 8 7 4 2 3 3 3 665 0.1uf 12 vb 16 15 9 6 2 11 7 3 8 5 1 19 22 26 signal gnd upper a upper b lower b upper c lower c vsd over current limit out +5v 500 lf111 op77 +15v 0.01 uf 0.01uf -15v r var 2k 25k 1k 25k 1k 2 7 4 6 3 23 24 25 20 21 18 17 vua vlpi vlpo vo a vo b vo c vcc a vcc b vcc c vss a vss b vss c gnd a gnd b gnd c vla vub vlb vuc vlc vsd 0.015 ? 5 1w 0.1uf phase a out (16v) 1n966a 1.6k tip61c +28v 2w phase b out phase c out 220-1,000 uf return 10w non-ind. lower a note: 30k - (750 x io) 0.375 x io r var = figure 9. typical optocoupler application
9 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 pwr-82331 power dissipation (see figure 11) there are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and flyback diode losses. v cc = +140 v (bus voltage) i oa = 20 a (see figure 11); i ob = 30 a; (see figure 11) ton = 20 s (see figure 11); t= 40 s (period) ron = 0.1 ? (on-resistance see table 2, i o = 30 a,t c = +25 c) ts1 = 250 ns (see figure 11); ts2 = 250 ns (see figure 11) fo = 25 khz (switching frequency) v f is the diode forward voltage, table 2, i o = 30 a, t c = +25 c v f (avg) = +1.15 v; i f is the diode forward current 1. conduction losses (p c ) pc = (i motor rms ) 2 x ron pc = (17.80 a) 2 x (0.1 ?) pc = 31.68 watts 2. switching losses (ps) ps = [vcc (i oa (ts1) + i ob (ts2)) fo] /2 ps = [140 (20 (250 ns) + 30(250 ns))25k]/2 ps = 21.88 watts 3. flyback diode losses (p df ) p df = i f (avg) x v f (avg) i f (avg) = [(i ob + i oa ) /2] /2 = [(30 + 20)/2]/2 = 12.5 a pdf = 12.5 a x 1.15 v pdf = 14.38 watts transistor power dissipation (p q ) to calculate the maximum power dissipation of the output tran- sistor as a function of the case temperature use the following equation. (reference figure 20 to ensure you don ? t exceed the maximum allowable power dissipation of each transistor.) p q = p c + p s total hybrid power dissipation (p total ) to calculate total power dissipated in the hybrid use: 6 p total = [ p qi + p dfi ] where i = each transistor or diode. i = 1 figure 11. output characteristics PWR-82333 power dissipation (see figure 11) there are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and flyback diode losses. v cc = + 270 v (bus voltage) i oa = 20 a (see figure 11); i ob = 30 a; (see figure 11) ton = 50 s (see figure 11); t=100 s (period) v ce(sat) = 3.8 v ( see table 2, i o = 30 a,t c = +25 c) ts1 = 300 ns (see figure 11); ts2 = 300 ns (see figure 11) fo = 10 khz (switching frequency) v f is the diode forward voltage, table 2, i o = 30 a, t c = +25 c v f (avg) = +1.70 v; i f is the diode forward current 1. conduction losses (p c ) pc = (i motor rms ) x v ce(sat) pc = (17.80 a) x (3.8 v) pc = 67.64 watts 2. switching losses (ps) ps = [vcc (i oa (ts1) + i ob (ts2)) fo] /2 ps = [ 270 (20 (300 ns) + 30 (300 ns))10k]/2 ps = 20.25 watts 3. flyback diode losses (p df ) p df = i f (avg) x v f (avg) i f (avg) = [(i ob + i oa ) /2] /2 = [(30 + 20)/2] /2 = 12.5 a p df = 12 5 a x 1.70 v p df = 21.25 watts transistor power dissipation (p q ) to calculate the maximum power dissipation of the output tran- sistor as a function of the case temperature use the following equation. (reference figure 20 to ensure you don ? t exceed the maximum allowable power dissipation of each transistor.) p q = p c + p s total hybrid power dissipation (p total ) to calculate total power dissipated in the hybrid use: 6 p total = [ p qi + p dfi ] where i = each transistor or diode. i = 1
10 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 ground connections layout and external components important: the following layout guidelines and required external components are critical to the proper operation of these motor drives. external connections can be easily made to the hybrid by any of the following methods: solder a wire around each pin. use pin extenders to raise the height of each pin so a print- ed circuit board can be mounted on top of the hybrid. use a printed circuit board with a cutout that will enable the printed circuit board to slide over the pins. permanent damage will result to the motor drive if the user does not make the following recommended ground connec- tions that will ensure the proper orientation of the hybrid. the vb and logic grounds are on pins 19, 22 and 26 (gnd). the vss connections for the output stage are on pins 1, 5, and 8 (vss). to prevent damage to the internal drive circuitry, the differential voltage between the gnd (pins 19, 22, 26) and vss (pins 1, 5, 8) must not exceed 3 v max, dc or peak. this includes the combined voltage drop of the associated ground paths and the voltage drop across rsense (see fig- ure 12). for example, a value for rsense of 0.025 w will give a voltage drop of +1.25 v at 50 a and allow enough margin for the voltage drop in the ground conductors. locate rsense 1" - 2" maxi- mum from the hybrid. it is critical that all ground connections be as short, and of lowest impedance, as the system allows. c1, c2, and c3 are 1 mf, +10 v ceramic capacitors that provide a low ac impedance between vss pin and gnd. you must use one capacitor for each vss pin-to-gnd connection (total of three capacitors in all), these capacitors are independent of the type of drive scheme used. (i.e., trapezoidal or sinusoidal drive). since placement of these capacitors is critical, place these capacitors across the hybrid, if possible. please note, on figure 12, that c1, c2, and c3 must go directly from terminal-to-terminal on the hybrid - do not daisy chain along the ground return. c4, c5, and c6 are the 0.1 mf ceramic bypass capacitors that suppress high frequency spiking. the voltage rating should be two times the maximum system voltage. these capacitors should be located as close to the hybrid as possible. care must be taken to control the regenerative energy produced by the motor in order to prevent excessive spiking on the vcc line. accomplish this by placing a capacitor or clamping diode between the vcc and the high-power ground return. figure 12. pwr-82331/33 ground connections c1, c2, c3 = 1 f, 10 v ceramic capacitors c4, c5, c6 = 0.1 f, ceramic capacitors c7 = 0.01 f, 100 v ceramic capacitors c7 = 0.01 f, 50 v ceramic capacitors
11 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 figure 13a. pwr-82331 typical forward voltage drop of flyback diodes figure 14a. pwr-82331 typical on resistance variation with temperature figure 13b. PWR-82333 typical forward voltage drop of flyback diodes figure 14b. PWR-82333 typical v ce(sat ) variation with temperature
12 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 figure 15a. pwr-82331 typical output on voltage drop versus output current figure 16. pwr-82331/82333 typical quiescent bias current versus bias voltage figure 15b. PWR-82333 typical output on voltage versus output current
13 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 0 operating frequency, fo (khz) bia s c urrent , i b ( m illiam p s) figure 17a. pwr-82331 typical bias current versus bias voltage at fo = 30 khz figure 17b. PWR-82333 typical bias current versus bias voltage at fo = 10 khz figure 18a. pwr-82331 bias current versus operating frequency figure 18b. PWR-82333 bias current versus operating frequency
14 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 figure 19a. pwr-82331 maximum allowable continuous output current versus case temperature figure 20. pwr-82331/82333 maximum allowable power dissipation of each output transistor versus case temperature figure 19b. PWR-82333 maximum allowable continuous output current versus case temperature
15 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 mounting the package bolts to part of the chassis or even the motor assembly itself, depending on system requirements. in applica- tions where this isn ? t convenient, the hybrid can be mounted to its own heatsink. the heat transfer in the hybrid is from semi- conductor junction to the bottom of the hybrid case. the flatness and maximum temperature of this mounting surface are critical to proper performance and reliability, because this is the only method of dissipating the power created in the hybrid. use a mounting surface flatness of 0.004 inches/inch maximum. this interface can be improved with the use of a thermal compound or pad. the heatsink should be designed to insure that the case temperature does not exceed +125 c. table 4. pin assignments pin function pin function 1 v ss c 26 gnd 2 v o c 25 v uc 3 v cc c 24 v lc 4 n/c 23 v sd 5 v ss b 22 gnd 6 v o b 21 v ub 7 v cc b 20 v lb 8 v ss a 19 gnd 9 v o a 18 v ua 10 n/c 17 v la 11 v cc a 16 v lpi 12 v b 15 v lpo 13 v z 14 n/c notes: 1. pins 3, 7, and 11 are internally connected. 2. pins 19, 22 and 26 are internally connected. figure 21. pwr-82331/82333 mechanical outline uppers inputs outputs v ua v uc v la v lc v s d v lb v o a v o c v o b v ub 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 h z z z z z z z z z z z z z z z h h h h h h h h h h h h h h h z h h h h h z l l l l h l l l l l l l l l h l l l h l l l l l l z l l 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 lowers control table 3. input-output truth table h = high level, l = low level, x = irrelevant, z = high impedance
16 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 standard ddc processing mil-std-883 test method(s) condition(s) inspection 2009, 2010, 2017, and 2032 ? seal 1014 a and c temperature cycle 1010 c constant acceleration 2001 a burn-in 1015, table 1 ? ordering information pwr-8233x-xx0x supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection blank = none of the above process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55 c to +125 c 2 = -40 c to +85 c 3 = 0 c to +70 c 4 = -55 c to +125 c with variables test data 5 = -40 c to +85 c with variables test data 8 = 0 c to +70 c with variables test data rating: 1 = 200 v using mosfets 3 = 500 v using igbts *standard ddc processing with burn-in and full temperature test ? see table below.
17 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 notes:
notes: 18 data device corporation www.ddc-web.com pwr-82331 and PWR-82333
19 data device corporation www.ddc-web.com pwr-82331 and PWR-82333 notes:
20 m-07/01-0 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7677 or 7381 headquarters, n.y., u.s.a. - tel: (631) 567-5600 ext. 7677 or 7381, fax: (631) 567-7358 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u

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